Extracting stabilizer parity checks from ancilla qubits every 400 ns to correct bit-flip (X) and phase-flip (Z) physical errors before they corrupt logical data.
To keep pace with physical superconducting gate speeds, decoders must solve graph-matching problems in under 1 microsecond. Our pipeline implements parallelized Union-Find cluster growth on Xilinx UltraScale+ FPGAs, delivering decoded error correction vectors in 380 nanoseconds.
Rather than physically moving logical qubits across a chip, the hypervisor alters local stabilizer definitions along the boundary between two surface patches. This merges or splits logical qubits via non-destructive measurements, enabling two-qubit logical gates with zero physical movement.